View MC33285DR2_1055348.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor Advance Information
Document Number: MC33285 Rev. 5.0, 2/2007
Dual High-Side TMOS Driver
A single input controls the 33285 in driving two external high-side NChannel TMOS power FETs controlling incandescent or inductive loads. Pulse Width Modulated (PWM) input control to 1.0 kHz is possible. The 33285 contains a common internal charge pump used to enhance the Gate voltage of both FETs. An external charge capacitor provides access to the charge pump output. Both external FETs are protected against inductive load transients by separate internal source-to-gate dynamic clamps. The power FETs are protected by the 33285 with short-circuit delay time of 800 s. The device is designed to withstand reverse polarity battery and load dump transients, encountered in automotive applications. Features * PWM Capability * Power TMOS Number One (OUT1) Short-Circuit Detection and Short-Circuit Protection * Voltage Range 7.0 V 40 V * Extended Temperature Range from -40C 125C * Load Dump Protected * Overvoltage Detection and Activation of OUT2 During Overvoltage * Single Input Control for Both Output Stages * Capacitor Value of 100 nF Connected to Pin CP * Analog Input Control Measurement Detection * OUT1 LOAD Leakage Measurement Detection * Pb-Free Packaging Designated by Suffix Code EF
33285
HIGH-SIDE TMOS DRIVER
D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-PIN SOICN
ORDERING INFORMATION
Device MC33285D/R2 MCZ33285EF/R2 Temperature Range (TA) -40C to 125C Package
8 SOICN
VCC
33285
VCC CP OUT2 DRN
VPWR
Input Control
IN GND
OUT1 SRC Motor
Figure 1. 33285 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIGN Kl.30 CP
VCC
CCP
+ VREF R S
Oscillator and Divider
Charge Pump
DRN
Bandgap
Rthr ION2 ION1
tLDDET
Load Dump Detection
IN
THRIN2
OUT2
tOUT2ECT
VOUT2-VDRN> VTH2
RQ S IOUTN2
VOUT1-VSRC> VTH1
+ +
OUT2 Activation Time
OUT1
THRIN1
GND
OC Detection
IOUTN1
M
+ -
RQ S
tOCDET Start tOCDET SCPC
SRC
Figure 2. 33285 Simplified Internal Block and Typical Applications Diagram
33285
2
Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
SRC OUT1 DRN OUT2
11
88 77 66 5
5
IN GND VCC CP
22
33
44
Figure 3. 33285 Pin Connections Table 1. 33285 Pin Definitions
Pin Number 1 2 3 4 5 6 7 8
Pin Name SRC
Formal Name Source Output 1 Drain Output 2 Charge Pump Voltage Power Supply Ground Input
Definition OUT2 external FET Source connection This pin is output number 1 OUT1 and OUT2 external FET Drain connection This pin is output number 2 External capacitor connection for internal the Charge Pump Battery supply voltage This is the ground pin. Voltage level sensitive input for OUT1 and OUT2
OUT1
DRN OUT2 CP VCC GND IN
33285
Analog Integrated Circuit Device Data Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Maximum Voltage at Pins OUT1 and OUT2 Maximum Voltage at Pin CP Input Voltage VI at DRN Input Voltage VI at SRC Input Voltage at Pin VCC Input Voltage at Pin IN. Condition: -2.0 V < VVCC < 40 V Operational Voltage VVCC at Pin VCC THERMAL RATINGS Storage Temperature Operating Ambient Temperature Peak Package Reflow Temperature During Reflow (1), (2) VOUT VCP VDRN VSRC VCC VIN VVCC VVCC + 20 50 -2.0 to 40 -5.0 to 40 -2.0 to 40 -2.0 to VVCC 7.0 to VI V V V V
V
Symbol
Value
Unit
V V
TSTG TA
TPPRT
-40 to150 -40 to 125 Note 2
C C C
Notes 1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33285
4
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions TA from -40C 125C, VCC from 7 V 20 V, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic OVERVOLTAGE AND OVER CURRENT Load Dump Activation Time Error Voltage Threshold SRC PIN 1 Leakage Current Leakage Current Detection Time DRN PIN 3 Operating Current (7.0 V < VDRN < 20 V) Leakage Current (0 V < VDRN < 20 V, VVCC < 4.0 V) OUT1, PIN 2, AND OUT2 PIN 4 Output ON Voltage. Charge Pump ON Turn OFF Current, VOUT > 0.5 V VCC PIN 6 Supply Voltage Range Quiescent Supply Current at VCC = 20 V IN PIN 8 Input Low Voltage OUT1 Input High Voltage OUT1 Input Hysteresis OUT1 and OUT2 Input Pull Down Current, 0.7 V < VIN < 6.0 V Open Input Voltage Input Low Voltage OUT2 Input High Voltage OUT2 VIL VIH VHYS IIN VIOP VIL2 VIH2 -- 1.7 0.4 7.5 -- -- 3.9 -- -- -- 15 -- -- -- 0.7 -- -- 16.5 0.7 3.0 -- V V V A V V V VCC ICC 7.0 -- -- -- 40 10 V mA VON IOUTOFF -- 66 -- 110 VCC + 15 154 V A IDRN ILEAK-DRN -- -5.0 -- -- 1.5 5.0 mA A ILCDET tLCDET 15 130 30 200 50 270 mA A Symbol Min Typ Max Unit
tOUT2ACT VDRN - VSRC
300 1.12
460 --
620 1.44
ms V
33285
Analog Integrated Circuit Device Data Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA from -40C 125C, VCC from 7 V 20 V, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic OVER VOLTAGE AND OVER CURRENT Load Dump Detection Time Over Current Detection Time OUT1 PIN 2, AND OUT2 PIN 4 Turn ON Time, OUT1: 8.0 nF, 10 A; OUT2:16 nF, 10 A -7.0 V < VCC < 10 V, VOUT > VCC + 7.0 -10 V < VCC < 20 V, VOUT > VCC + 11 tON -- -- -- -- 1.5 1.5 ms tLDDET tOCDET 250 520 400 800 550 1080 s s Symbol Min Typ Max Unit
33285
6
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The power FETs are turned ON by charging their gate capacities with a current flowing out of pins OUT1 and OUT2. During PWM, the values of table below are guaranteed. They are measured with 8.0 nF on OUT1 and 16 nF on OUT2. Test condition VIN: ramp 0 V 2.5 V or 2.5 V 5.0 V.
IN
5.0 V 2.5 V
IN
THRIN2 THRIN1 VOUT1 VVCC + 7.0
VCCP
VOUT2
VOUT2
20 ms
5.0 V 2.5 V
IN
0V VOUT1MAX
IN
2.5 V VOUT2MAX VOUT2
VOUT1 0V 0V tON1 tON2 0 tON3 0 tON1 tON3 tON2
VOLTAGE VVCC 7.0 V < VVCC < 10 V 10 V < VVCC < 20 V 20 V < VVCC < 40 V
MINIMUM VOUT1, OUT2 AFTER TON1 = 100 SEC VVCC - 0.7 V VVCC - 0.7 V VVCC - 0.7 V
MINIMUM VOUT1,OUT2 AFTER TON2 = 1.0 SEC VVCC + 5.95 V VVCC + 9.35 V
MINIMUM VOUT1,OUT2 AFTER TON3 = 1.5 SEC VVCC + 7.0 V VVCC + 11 V
Figure 4. Turn On Behavior Turn Off Characteristics The output voltages at OUT1 and OUT2 are limited by The power FETs on OUT1 and OUT2 are turned OFF by controlling the current sources ION1, ION2 to avoid current discharging the gate capacity with the constant discharge flowing through the external or the internal zener diode. current IOUTOFF. When voltage power supply plus threshold voltage * Discharge current IOUTxOFF is IOUTxOFF = 110 A (VCC + VTH) is reached, the current sources are turned OFF. condition: VOUT x > 0.5 V ( VIN < VTHRxIN ) * Threshold VTH1 for OUT1 output voltage control is 7.0 V < VTH1 < VZ * Test conditions for switching OFF the power FETs: * Threshold VTH2 for OUT2 output voltage control is 1. IN open 7.0 V < VTH2 < 15 V 2. Stages disabled via pin IN 3. Stage OUT1 disabled by an over current error
33285
Analog Integrated Circuit Device Data Freescale Semiconductor
7
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES INTRODUCTION
The 33285 contains only one charge pump for two outputs.The outputs, OUT1 and OUT2, are switched ON and OFF by the input (IN) .There are three ways to control the outputs: OUT1 can be switched alone OUT1 and OUT2 can be switched together OUT2 can be switched when OUT1 is already on In the last case, the voltage drop on OUT1 when charging OUT2 is limited. The external capacitor (CCP) connected to the CHARGE PUMP (CP) pin is used to store the charge continuously delivered by the charge pump. The voltage on this pin is limited to a maximum value VCPMAX. Both outputs are sourced with a constant current from CCP to switch them ON. Additionally, the gates of the power FETs are precharged from voltage power supply (VCC) to prevent CCP from being discharged by a voltage on OUT1 or OUT2, is still lower than VVCC. The values of the output voltages are limited to VOUT1MAX and VOUT2MAX. The power FET on OUT1 is protected against an exceeded gate-source voltage by an internal zener diode. Channel One protects the N-Channel power FET on OUT1 undercurrent and short-circuit conditions. The drain-source voltage of the FET on OUT1 is checked if Channel One is switched ON. The internal error voltage threshold determines the maximum drain-source voltage allowing the power FET to stay in the ON state. If the measured drain-source voltage exceeds the internal error voltage threshold, the output of the short-circuit protection comparator (SCPC) is enabled. If the output of the SCPC is active longer than tOCDET, output OUT1 is switched OFF. After switching OFF the power FET on OUT1 by an shortcircuit condition, the power FET can only be turned ON again by the input IN. When switching OFF the power FETs their gate capacities are discharged by a constant current, IOUTOFF. If the input IN is disconnected, the 33285 outputs, OUT1 and OUT2, are in the OFF state. If overvoltage occurs on the DRAIN (DRN) pin for a time period longer than tLDDET, OUT2 is switched ON for the time tOUT2ACT. In an overvoltage condition OUT1 is OFF if IN is below VIH.
INTERNAL ZENER DIODE
An on-chip zener diode is placed between OUT1 and The SOURCE (SRC). Design guarantees VZ > VTH1. Zener clamping voltage between OUT1 and SRC is VTH1 < VZ < 20 V
PWM CAPABILITY
The CPIC2 is PWM capable on OUT2. The loss of charge ON CCP when switching ON OUT2 is refreshed until the Start on the next PWM cycle to a value sufficient to guarantee the specified turn ON behavior. The PWM capability is measured with a test circuit and load conditions: * PWM cycle is period T = 20 ms ; OUT2 is switched ON from 10 to 90 percent of T * Test condition VIN ramps 2.5 V 5.0 V according to PWM cycle defined above
CROSS TALK BETWEEN OUT1 AND OUT2
If output OUT2 is switched ON while OUT1 is already ON, the voltage drop occurring on OUT1 is limited. Voltage drop on OUT1: * 10 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V * 7.0 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V Each time OUT1 is switched ON, a current ILCDET is sourced out of the SRC pin for the time tLCDET to check if there is an external leakage current on that node in the application. The high-side switch on OUT1 is turned ON only if the test is successful.
33285
8
Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
D SUFFIX EF SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASB42564B ISSUE U
33285
Analog Integrated Circuit Device Data Freescale Semiconductor
9
REVISION HISTORY
REVISION HISTORY
REVISION 4.0
DATE 9/2006 * * * * *
DESCRIPTION OF CHANGES Implemented Revision History page Converted to Freescale format Added part number MCZ33285EF (Pb-FREE) to Ordering Information Added Peak Package Reflow Temperature During Reflow (1), (2) to Maximum Ratings Added notes (1) and (2)
5.0
2/2007
33285
10
Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
33285
Analog Integrated Circuit Device Data Freescale Semiconductor
11
REVISION HISTORY
33285
12
Analog Integrated Circuit Device Data Freescale Semiconductor
How to Reach Us:
Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http:// www.freescale.com/epp.
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2007. All rights reserved.
MC33285 Rev. 5.0 2/2007

▲Up To Search▲

Price & Availability of MC33285DR2

	To Download MC33285DR2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .